Integrated circuit cooling using embedded peltier micro-vias in substrate

ABSTRACT

A semiconductor device package and method for manufacturing the same, includes a semiconductor substrate including a plurality of embedded thermoelectric couples. The embedded thermoelectric couples can be in trenches and extend partially into the substrate from the handle side of the substrate. An n-type pillar and a p-type pillar are electrically connected using a conducting contact plate to form each of the partially embedded thermoelectric couples. A series connection layer electrically connects the plurality of thermoelectric couples on the handle side. A power source provides electrical current to the series connection layer allowing current to flow through the plurality of the series connected thermoelectric couples. A heat sink is positioned adjacent to the connected thermoelectric couples for transferring heat away from the device side to the heat sink using the thermoelectric couples.

BACKGROUND

The present disclosure relates to a semiconductor structure and methodfor semiconductor fabrication. Integrated circuits (IC(s)) can generateheat in a semiconductor package. Heat within the semiconductor packagecan cause undesirable consequences in the semiconductor package, such asa deleterious impact on the functioning of devices within the IC, andfailure of components. Cooling techniques for the IC can include a heatsink or other cooling mechanisms requiring power from the IC and thesemiconductor package. Three dimensional integrated circuits areparticularly prone to undesirable heat buildup within the device orpackage.

SUMMARY

According to an embodiment of the invention, a semiconductor devicepackage includes a plurality of thermoelectric couples embedded in asemiconductor substrate. The thermoelectric couples each includethermoelectric pillars positioned opposite one another in each of aplurality of trenches in the substrate. Each of the trenches define anopening in a handle side of the substrate which is opposite from adevice side of the substrate. The pillars extend partially into thesubstrate from the handle side of the substrate, and the opposingpillars are N type and P type materials, respectively. A thermallyconducting isolation layer is along a perimeter of the trenches andalong outer sides of the pillars. A conductive plate electricallyconnects the n type and p type pillars. A series connection layerelectrically connects the plurality of thermoelectric couples on thehandle side of the substrate for receiving a voltage via the seriesconnection layer. A heat sink is positioned adjacent to thethermoelectric couples for transferring heat away from the device sideof the substrate to the heat sink using the thermoelectric couples.

According to another embodiment of the invention, a method formanufacturing a semiconductor substrate includes forming trenchesextending partially into a substrate from a handle side of the substratewhich is opposite from a device side of the substrate. The trenchesdefine an opening in the handle side of the substrate for each of thetrenches. A thermally conducting isolation layer is deposited along aperimeter of the trenches and is positioned along outer sides of thepillars. N-type pillars and p-type pillars are formed opposite oneanother and on opposite sides of each of the trenches to formthermoelectric couples. A conductive plate is formed for electricallyconnecting the N-type and the P-type pillars. A series connection layeris formed which electrically connects the plurality of thermoelectriccouples for receiving a voltage via the series connection layer. A heatsink is positioned adjacent to the thermoelectric couples to transferheat away from the device side of the substrate to the heat sink usingthe thermoelectric couples.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof illustrative embodiments thereof, which is to be read in connectionwith the accompanying drawings. The various features of the drawings arenot to scale as the illustrations are for clarity in facilitating oneskilled in the art in understanding the invention in conjunction withthe detailed description. In the drawings:

FIG. 1 is a cross sectional side elevation view of a substrate having adevice level/layer, the substrate includes a series of thermoelectriccouples, and the substrate communicates with a heat sink, according toan embodiment of the disclosure;

FIG. 2 is a cross sectional side elevation view of a substrate having adevice level layer, a trench, and through silicon vias, according to anembodiment of the disclosure;

FIG. 3 is a cross sectional side elevation view of a substrate having adevice level/layer and through silicon vias, according to an embodimentof the disclosure;

FIG. 4 is a cross sectional side elevation view of the substrate shownin FIG. 3, having a trench;

FIG. 5 is a cross sectional side elevation view of the substrate shownin FIG. 4 having a liner over the trench;

FIG. 6 is a cross sectional side elevation view of the substrate of FIG.5 having a barrier/seed layer;

FIG. 7 is a cross sectional side elevation view of the substrate of FIG.6 having a pillar formed in the trench;

FIG. 8 is a cross sectional side elevation view of the substrate of FIG.7 having another pillar formed in the trench;

FIG. 9 is a cross sectional side elevation view of the substrate of FIG.8 having conductive elements formed in the trench and on the handle sideof the substrate;

FIG. 10 is a cross sectional side elevation view of the substrate ofFIG. 9 as a final structure;

FIG. 11 is a cross sectional side elevation view of a substrate similarto the substrate shown in FIG. 2, having a buried interconnect area,according to an embodiment of the disclosure;

FIG. 12 is a cross sectional side elevation view of a substrate forminga buried interconnect area;

FIG. 13 is a cross sectional side elevation view of the substrate ofFIG. 12 having through silicon vias in the substrate;

FIG. 14 is a cross sectional side elevation view of the substrate ofFIG. 13 with the substrate flipped over;

FIG. 15 is a cross sectional side elevation view of the substrate ofFIG. 14 having thermoelectric pillars formed in the substrate andconnected to the buried interconnect area;

FIG. 16 is a cross sectional side elevation view of an integratedcircuit package, according to an embodiment of the disclosure, having asubstrate similar to the substrate shown in FIGS. 1 and 10 connected toanother substrate;

FIG. 17 is a cross sectional side elevation view of the package shown inFIG. 16 having a heat sink; and

FIG. 18 is a cross sectional side elevation view of an integratedcircuit package according to an embodiment of the present disclosure,including a heat sink on a substrate similar to the package shown inFIG. 17, but without through silicon vias in the substrate, andincluding an external power/voltage source.

DETAILED DESCRIPTION

Referring to FIG. 1, a semiconductor substrate 10 according to anembodiment of the disclosure is discussed herein. One side of thesubstrate 10 includes a device layer or level 14 (also referred to as anactive device side), and the opposite side of the substrate 10 iscoupled to a heat sink 20. Thermoelectric couples 30 each include atrench created from the handle side (the heat sink side) of thesubstrate 10. The thermoelectric couples 30 include a cooling conductingplate 34, which, for example, may be comprised of metal, for example,copper, or Tungsten etc., and is embodied as a copper cooling plate inthe embodiment of FIG. 1. An isolation layer 38 surrounds thethermoelectric couples 30, that is, the isolation layer extends along aperimeter of the trench. The thermoelectric couples 30 include an N-typethermoelectric material pillar 42 and a P-type thermoelectric materialpillar 44 in the trench separated by the conductive contact plate 34 forheat transfer. The N-type and P-type thermoelectric materials can bedeposited in the trenches. The N-type and P-type material pillars arecomprised of thermoelectric materials, for example, Bismuth Telluride,Lead Telluride and other materials. An area of the trench definedbetween the N-type thermoelectric pillar 42 and the P-typethermoelectric pillar 44, and over the conducting plate 34 can beoptionally filled with a filler 52. A series connection layer 56electrically connects the thermoelectric couples on the handle side ofthe substrate, and enables current flow, for example, a positive 46 to anegative 48 current flow. The series connection layer 56 is positionedbetween the trenches and the heat sink 20, and runs along the length ofthe substrate to connect the thermoelectric couples on the handle(trench opening) side of the substrate.

The embodiment shown in FIG. 1 of the present disclosure therebydescribes an integrated circuit having a cooling technique whichincludes thermoelectric couples 30 having thermoelectric pillars intrenches extending partially into the substrate 10 and connected inseries within the substrate with a direct or buried link. For example,the trench can extend a small depth from the handle side of thesubstrate. Alternatively, the trench can extend in the substrate untilclosely reaching the device side or device level in the substrate.Preferably, the trench will not penetrate the device level of thesubstrate. An example depth of the trench can include a shallow trenchthat can accommodate the features of the thermoelectric pillars as inthe present disclosure, to a trench depth that is close to the activelayer or adjacent the active layer.

The plurality of the trenches can be connected in series using aconductive path, the series connection layer 56, formed on the handleside of the device as shown in FIG. 1, and connected to an appropriatevoltage source (power source) for active cooling. The thermoelectriccouples can communicate with a heat sink on the handle side of thesubstrate (as shown in FIGS. 16 and 17).

The device layer 14 of the substrate can be connected to the othersubstrates within an IC package (shown in FIGS. 16 and 17). Connectionfeatures, such a ball grid, or connection pads, can be used forelectrical connections within an IC package, for example, from thedevice level in the IC package. The method and structure of the presentdisclosure, using the thermoelectric couples and electrical currentflow, makes use of a thermoelectric effect to transfer heat from thedevice layer 14 of the substrate to the heat sink 20 communicating witha handle side (opposite side from the device layer) of the substrate.

Referring to FIG. 2, in one embodiment according to the presentdisclosure, a substrate 100 is similar to the substrate shown in FIG. 1,and similar elements have the same reference numbers. The substrate 100includes a device level or layer 14. Connection pads 104 are connectedto the device layer and communicate with conductive levels 108 in theactive layer 14. The connection pads 104 are comprised of anelectrically conductive material. Through vias 112 (i.e., throughsilicon vias (TSVs)) connect the active layer 14 to the connection layer56 (shown partially in FIG. 2) on a handle side 116 of the substrate100. The trench 30 includes an isolation layer 38 along the opposingsides of the trench 30, which extends between the handle side 116 of thesubstrate 100 and the connection layer 56. The isolation layer is alsodeposited along the side walls of the vias, as shown in FIG. 2.

An N-type thermoelectric pillar 120 material is deposited on one side ofthe trench 30, and can comprise N-type Bismuth Telluride (Bi2 Te3). AP-type thermoelectric pillar 124 material is deposited on an oppositeside of the trench 30 from the N-type pillar in the trench 30. TheP-type pillar can comprise P-type Bismuth Telluride (Bi2 Te3). A trenchlayer 128 is between the N-type and P-type pillar and is positioned atthe bottom of the trench 30. The trench layer 128 may be comprised of,for example, copper, or tungsten, which are electrically conducting andthermally conducting.

Referring to FIGS. 3-10, a process flow for manufacturing asemiconductor device, according to an embodiment of the disclosure, isdiscussed below. Similar elements in the embodiments shown in FIGS. 1and 2 have the same reference numerals. Referring to FIG. 3, a substrate200 includes through vias 112 connecting the handle side 116 of thesubstrate to the active layer 14. An oxide layer 38 is initially presenton the backside of the wafer.

Referring to FIG. 4, a trench 210 is etched in the substrate 200.Referring to FIG. 5, a liner 214 is formed along the perimeter of thetrench 210 which can be selectively deposited. The liner can becomprised of material which has good thermal conductivity butelectrically isolating. Referring to FIG. 6, a barrier/seed layer 218 isdeposited over the liner 214 along the handle side of the substrate andalong the perimeter of the trench 210. The barrier/seed layer can becomprised of materials, for example, Titanium (Ti), Ruthenium (Ru), orTitanium Nitride (TiN), which also have good thermal conductivity.

Referring to FIG. 7, a resist layer 222 is deposited over the handleside 116 of the substrate 200. Lithography and reactive ion etching canbe used to form a trench in the resist. An n-type pillar 230 is formedon one side of the trench. The n-type pillar can be comprised of aN-type thermoelectric material, e.g., N-type Bismuth Telluride (Bi2Te3). Referring to FIG. 8, the resist has been removed partly and aP-type pillar 234 is formed on the opposite side of the trench from theN-type pillar. The N-type pillar can be comprised of P-typethermoelectric material, e.g., P-type Bismuth Telluride (Bi2 Te3).

Referring to FIG. 9, a resist layer 222 (as an etch barrier) isdeposited to protect the N-type and P-type thermoelectric pillars. Theresist layer 222 is etched away to deposit a conductive layer 238 at theareas shown in FIG. 9. The conductive layer 238 can be comprised of, forexample, copper, or tungsten, which are electrically conducting to allowpassage of current between the thermoelectric pillars. Referring to FIG.10, the resist 238 and the barrier/seed layer 218 have been partiallyremoved, for example, by etching, and the final substrate 250 with thethermoelectric couple 254 is shown.

FIG. 1 shows multiple trenches that are shown in FIG. 10 (and in FIGS.16 and 17 below). The present disclosure thereby describes an integratedcircuit having a cooling technique which includes thermoelectric coupleshaving thermoelectric pillars extending partially into the substrate andconnected in series within the substrate with a direct or buried link.The plurality of the thermoelectric couples (shown in FIG. 1) can beconnected in series using a conductive path formed on the handle side ofthe device as shown in FIG. 1, and connected to an appropriate voltagesource for active cooling. The thermoelectric couples and pillarscommunicate with a heat sink on the handle side of the substrate.

Referring to FIG. 11, another embodiment according to the presentdisclosure includes a substrate 300 including N-type and P-typethermoelectric pillars 304, 308, respectively. Both thermoelectricpillars can be comprised of any of the known thermoelectric materials(e.g., Bi2 Te3). A buried interconnect area 312 can include implantedmetal in the substrate. The buried interconnect area 312 communicateswith the pillars 304, 308.

Referring to FIGS. 12-15, a process flow for manufacturing the substrate300 shown in FIG. 11 is discussed. Referring to FIG. 12, a resist layer320 is deposited over part of an active side 324 of the substrate exceptfor an area corresponding to an area of the substrate for an implantedconductor 330 to form a buried interconnect 340 (shown in FIG. 15).Referring to FIG. 13, the active level 14 can be formed on the activeside 324 of the substrate, and TSVs 112 formed in the substrate 300.

Referring to FIG. 14, the substrate 300 is shown flipped over so thatthe active level 14 is on the bottom in the drawing. Referring to FIG.15, pillars 304, 308 are formed from the handle side 116 of thesubstrate 300, and the substrate 300 is the same as shown in FIG. 11.The substrate 300 includes N-type and P-type pillars 304, 308. Theburied interconnect 340 has been formed within the substrate 300 andconnects the pillars 304, 308.

The voltage applied to the free ends of two different conductingmaterials, results in a flow of electricity through a series ofthermoelectric couples, and two semiconductors in series. Current flowsthrough the series electrical connection on the handle side (orbackside) of the substrate through the N-type thermoelectric pillar tothe conducting plate, to the P-type thermoelectric pillar andsubsequently to the heat sink. Since the thermoelectric couples are inseries (or daisy chained), the current flows though the all thethermoelectric couples connected in series. Peltier cooling causes heatto be absorbed from the vicinity of the conducting cooling plate, and tomove the absorbed heat to the other end of the substrate, i.e., to theheat sink. When current is forced through the unit (the substrate asshown in the figures), the electrons at one end absorb energy, whilethose at the other end release energy. Therefore with a continuouscurrent flow, heat is constantly absorbed at one end and released atanother end.

Referring to FIG. 16, an IC package 400, according to an embodiment ofthe present disclosure, includes similar features to previouslypresented embodiments which have the same reference numerals. The ICpackage 400 includes a second substrate 404. The second substrate 404 isconnected using solder balls 408 to a substrate 350 incorporating thefeatures of the present disclosure shown in FIG. 10 as the substrate250. The substrate 350 includes an active side 14 and a handle side 116.The trenches 412 of the substrate 400 are similar to those describedabove as trench 30, shown in FIGS. 1 and 2, and thermoelectric couple254 of substrate 250 shown in FIG. 10. In the IC package 400 of FIG. 16,the substrate 350, and its through vias are connected to the secondsubstrate 404 using the solder balls 408 and conductive pads 104.Referring to FIG. 17, the IC package 400 is shown attached to othersubstrates 460 (using solder balls 408), and a heat sink 470 ispositioned over the additional substrates 460 and the substrate 350. Theheat sink 470 is connected using a thermal interface material 474 (TIM)which enhances the heat transfer 478 from the substrate 350 and itstrenches 412 to the heat sink 470.

Referring to FIG. 18, another embodiment of an IC package 500, accordingto the present disclosure, has similar features to the package shown inFIGS. 16 and 17 with the same reference numerals for the same features.The IC package 500 includes a substrate 550, and trenches 412 which areshown in FIGS. 16 and 17. TSVs 112 shown in FIGS. 16 and 17, have beeneliminated in the substrate 550. Separate wiring (not shown) for currentflow through the substrate and pillars in the trenches can be utilized.

A heat sink 504 is posited over the trenches 412 of the substrate 550.The heat sink 504 is similar in structure and function to the heat sink470 shown in FIG. 17, however, the heat sink 504 has a series of fins508 for enhancing heat dissipation. The substrate 550 and trenchesreceive power from an electrical circuit 512 through the handle side ofthe substrate without using TSVs. The substrate 550 is connected to asecond substrate 404 as shown in FIG. 18.

Generally, according to the embodiments of the present disclosure, asemiconductor device package and method for manufacturing the sameincludes embedded thermoelectric couples in a semiconductor substrate.The thermoelectric couples can include trenches extending partially intothe substrate with N-type and P-type pillars extending into thetrenches. A thermally conducting isolation layer can be deposited in thetrenches. The isolation liner can be comprised of a material which has ahigh thermal conductivity but is electrically isolating. Thethermoelectric N-type and P-type pillars are electrically connectedusing a contact plate or conducting plate to form each of the partiallyembedded thermoelectric couples. A series connection layer electricallyconnects the plurality of thermoelectric couples on the handle side ofthe substrate. A power source provides electrical current to the seriesconnection layer formed, and provides current flowing through theplurality of the series thermoelectric couples. A heat sink ispositioned adjacent to the connected thermoelectric couples andtransfers heat away from the device side of the substrate.

The embodiments of the present disclosure do not require movingcomponents or cooling apparatus, such as liquid pumping which can beused to cool three dimensional ICs. The trenches increase surface areacontact with the substrate to enhance heat transfer to the heat sinkdevice to increase cooling of the IC package. The thermoelectric pillarsdo not use the area of the substrate for the device level (or devicelayer) side of the substrate, thus allowing the most efficient use ofthe device level.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

1. A semiconductor device package, which comprises: a plurality ofthermoelectric couples embedded in a semiconductor substrate, thethermoelectric couples each including thermoelectric pillars positionedopposite one another and extending into the substrate from a handle sideof the substrate being opposite from a device side of the substrate; thepillars extending partially into the substrate from the handle side ofthe substrate, the opposing pillars being N type and P type,respectively; a thermally conducting isolation layer along a perimeterof the trenches and along outer sides of the pillars; a conductive plateelectrically connecting the n type and p type pillars; a seriesconnection layer electrically connecting the plurality of thermoelectriccouples on the handle side of the substrate for receiving a voltage viathe series connection layer; and a heat sink positioned adjacent to thethermoelectric couples for transferring heat away from the device sideof the substrate to the heat sink using the thermoelectric couples. 2.The device of claim 1, further comprising: a power source for providingelectrical current to the series connection layer such that theelectrical current flows through the plurality of thermoelectriccouples.
 3. The device of claim 1, wherein the power source iselectrically connected to the series connection layer via throughsilicon vias.
 4. The device of claim 1, wherein the power sourceincludes a voltage source connected to the series connection layer,without the use of through silicon vias.
 5. The device of claim 1,wherein the conductive plate separates the n-type and the p-type pillarsdefining a bottom of each of the trenches opposite the openings of thetrenches in the handle side of the substrate.
 6. The device of claim 1,wherein the opposing pillars of the thermoelectric couples arepositioned in each of a plurality of trenches in the substrate, each ofthe trenches define an opening in a handle side of the substrate.
 7. Thedevice of claim 1, further comprising; a filler material deposited ineach of the trenches between the n-type and p-type pillars.
 8. Thedevice of claim 1, wherein the heat sink is a finned copper heat sink.9. The device of claim 1, wherein the series connection layer ispositioned between the thermoelectric couples and the heat sink.
 10. Thedevice of claim 1, further comprising: a power source for providingelectrical current to the series connection layer, such that theelectrical current flows through the plurality of thermoelectric couplesfrom each of the p-type pillars through the conducting plate to then-type pillars, respectively, and through the series of thermoelectriccouples. 11-20. (canceled)